The field of the present invention relates generally to electroplating processes used to produce metal deposits having precise microscopic features. In particular, the field of the invention relates to the fabrication of LIGA microstructures and metallization of semiconductor devices, or to any process wherein metal is electrochemically deposited into lithographically produced molds containing a multiplicity of microscopic cavities such as trenches and holes.
The present invention is particularly beneficial in producing uniform voidfree deposits under adverse circumstances where there are large variations in the size and areal density of mold cavities or when these cavities are much deeper than their lateral dimensions.
The primary target technologies of the present invention are: (1) fabrication of microdevices by the LIGA process and (2) metallization of semiconductor devices. Each of these processes is separately described below, followed by an explanation of manufacturing difficulties that are remedied by the present invention. A common aspect of both target technologies is the need for uniform void-free plating of microscopic features having high aspect ratios.
LIGA Technology
LIGA, an acronym from the German words for lithography, electroforming and molding, is a promising new process for producing metal microdevices having micron to millimeter features. In the first step of LIGA, a photoresist (photosensitive or photo-definable) material is exposed to high-energy radiation through a patterned mask. This photoresist is then developed in a chemical bath which preferentially dissolves the exposed regions. The developed photoresist, bonded or clamped to a conducting substrate, subsequently serves as a mold to be filled with metal by electrodeposition. After filling of the mold cavities is complete, the mold is usually dissolved by chemical etching, leaving only the desired metal structure or a collection of finely detailed metal parts still attached to the substrate. In some cases, the resulting metal structure is not the final product but rather serves as a mold or die in the final step of mass production by injection molding or embossing.
Currently under worldwide development, this process offers a means to manufacture high resolution, high aspect-ratio metal devices including microscale valves, motors, solenoid actuators, and gear trains. Such devices cannot be fabricated either by silicon micromachining or by precision machine tool operations. The depth dimension of a typical LIGA structure ranges from about 10 microns to a few millimeters. Since the mold is generally fabricated from a flat sheet of photoresist, the depth of all mold cavities and that of all electroformed features is generally the same in a single-layer device. However, the lateral dimensions and geometries of individual features may be widely variable and highly complex. Features having aspect ratios (depth to width) greater than 10 pose a challenge to conventional electroplating, particularly for feature depths greater than 100 microns.
The LIGA process is applicable to a broad range of enabling technologies which require high aspect ratio microstructures such as microscale pumps, motors, valves, micro actuators, switches, positioners, or the like. As such, the LIGA process is ideal for miniaturizing mechanical components used in sensing and process control, computer peripherals, automotive, medical, and aerospace and defense applications.
The total market for microdevices is growing very rapidly and is estimated to be between approximately $3 billion and $14 billion per year by the year 2000 The potential for high aspect ratio metal devices in the total microdevice market depends strongly on exploiting the unique capability of LIGA-like processes to produce high aspect ratio microstructures, and on reducing product costs through improved manufacturing methods. The aspects of the invention described herein provide a solution to several outstanding problems in the LIGA manufacturing process and so should make possible an increase in the future market share for metal devices or microstructures produced by this and related electrodeposition processes.
LIGA Deficiencies
One difficult problem in the LIGA process is nonuniform deposition of metal within the mold. In all electroplating processes, geometric irregularities give rise to nonuniform electric current densities. Since electric currents drive the electrodeposition process, nonuniform currents give rise to nonuniform metal deposition rates. For example, the corners of a rectangular region will always have a local current density that exceeds the mean value for the surface by a significant factor. As a result, deposition rates at these corners will be greater than the average rate. Similarly, a hole in an otherwise uniform surface, sharp bends in a linear feature, or parallel linear features of irregular spacing will also give rise to nonuniform deposition rates near the geometric irregularity.
In conventional electroplating practice, robbers and shields are employed to improve metal deposition uniformity on surfaces of irregular geometries. Robbers are electrically conducting elements placed near the deposition surface with the intent of locally altering the electric potential to produce a more uniform current flux over the surface. The shape, position and electric potential of the robber must be carefully selected to produce the desired effect. In contrast, shields are electrically insulating elements usually placed between the bath electrode and the deposition surface. Their purpose, however, is the same as that of a robber to locally alter the current density to obtain a more uniform deposition rate. Like robbers, shields must be carefully designed and placed to produce the desired benefit.
Because of the very small feature sizes of LIGA molds, shields and robbers are not practical for micro molding of complex three dimensional structures . In principle, robbers could be designed as part of the LIGA mold, but this would require many iterations of the robber design to effectively achieve uniform deposition over the many features present in a typical LIGA part. Further, such integral robbers would likely limit the range of possible designs for the LIGA device. Special shields also could be fabricated using lithographic methods, but again these would require many trial-and-error iterations to be highly effective. Since shields and robbers are not very practical for the LIGA process, other techniques must be pursued to ensure uniform deposition in the LIGA mold.
Current practice in LIGA manufacturing is largely to tolerate nonuniform deposition or to attempt to correct it in an iterative fashion. The mold is periodically removed from the plating bath and inspected. Areas experiencing excessive deposition rates are coated with an insulating paint to inhibit further deposition in those areas, and the mold is then returned to the bath for an additional period of plating. This cycle is repeated until all cavities in the mold are filled. This is a costly and time-consuming practice that is not well suited to the mass production of LIGA parts. Therefore, to successfully develop the LIGA process as a flexible and cost-effective manufacturing method, a method is needed for solving the problem of nonuniform deposition in the mold. What is also needed is a method for providing uniform deposition of metal for complex three-dimensional microstructures. It also would be advantageous to provide a method for fabricating a uniform metal layer which is scalable and applicable to nanometer through micron size microstructures and devices.
Metallization of IC Devices
As Integrated Circuit devices continue to shrink in size, metal interconnects become the dominant limitation in circuit speed. Interconnect areal dimensions must shrink in proportion to the semiconductor devices, which reduces their conductivity. In order to compensate for this loss in conductivity, interconnects must be made taller, requiring a large aspect ratio. Achieving this large aspect ratio without voids in the structure is difficult using existing electroplating and metallization technology. For these reasons, interconnects potentially represent the largest technology gap for future generations of IC devices.
Aluminum to Copper
As device sizes get smaller, the electrical properties of aluminum will no longer meet the new semiconductor industry requirements. Copper interconnects provide the potential advantages of lower ohmic resistivity and increased resistance to electromigration. Thus, the change from aluminum to copper will help to further reduce chip dimensions. However, as the first chips so bearing copper interconnects are beginning to enter the market, the copper connector pioneers are experiencing difficulties, with yields in some cases close to zero. Only, an isolated few in the technology reportedly have managed 50 percent yields.
Despite these difficulties, Cu is expected to be adopted in deep submicron VLSI metallization due to its lower resistivity than conventional Al alloys. To implement Cu interconnects, the damascene process will be employed to overcome the low etch raters in dry-etching of Cu. However, this approach requires Cu to be deposited void-free in trench and via structures with fairly high aspect ratios. Chemical vapor deposition (CVD) and electroplating are the two most promising techniques that could meet this requirement. These two processes produce Cu deposits having different microstructures and, hence, differing electromigration characteristics. However, in either CVD or electrodeposition, it is extremely difficult to achieve void-free filling of high aspect ratio trenches and vias. This is because excessive material deposition at the top of these cavities may close them off, leaving voids below. As will be seen, the present invention helps to remedy this problem and thereby improve process yields.
Damascene Process
The semiconductor industry currently employs a conventional method called the damascene process to build copper interconnections on chip devices. The term damascene is borrowed from the way the Arab sword smiths of medieval Damascus inlaid their famous weapons. A typical single damascene process proceeds along the following steps. First, the trenches for the interconnects are etched into the dielectric. Second, a Cu diffusion barrier such as Tantalum (Ta) or Tantalum Nitride (TaN) is deposited to protect against Cu diffusion into the dielectric or active silicon devices. Third, the trench is filled. This step can be done by one of the following methods; electroless plating, electroplating, Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). Finally, the excess Cu from the fill is removed by chemical mechanical polishing (CMP) to produce a planarized top surface.
If the fill is performed by CVD, it is extremely difficult to completely fill trenches and vias having aspect ratios greater than unity. Under ideal conditions of conformal deposition on all exposed surfaces, the deposition layers on the side walls grow uniformly toward one another leaving a progressively narrower void space. At the same time, the center void is filling from the bottom up. For aspect ratios less than one-half, the bottom-up filling will be complete before the side walls merge. At higher aspect ratios, however, the filling is completed by merging of the side walls, so any excess deposition near the top will cause closure before the bottom is filled completely. In the absence of a directional bias, deposition will generally occur preferentially near the top of the feature, since deposition near the bottom requires that material must be transported downward through a gap of progressively decreasing width. Thus, voids are likely to occur during CVD filling of trenches having aspect ratios greater than unity.
Alternatively, if the fill is performed by electrodeposition of Cu, it is first necessary to deposit a conducting xe2x80x9cseed layerxe2x80x9d, usually Cu, that is generally quite thin compared to the feature widths but thick enough to carry the electric current needed for electrodeposition. Since the seed layer generally covers all exposed surfaces, electrodeposition will later occur on all of these surfaces. Moreover, since current densities and Cu ion concentrations are generally greatest on the exposed wafer face and the upper sidewalls of trenches or vias, metal deposition rates will be greatest at these locations, closing the cavity tops before the bottoms are completely filled. This difficulty can be offset, in part, by using xe2x80x9cleveling agentsxe2x80x9d or plating inhibitors that are preferentially consumed in the regions of highest current near the top of the feature, but even this approach becomes less effective as feature depths and aspect ratios increase.
For these reasons, copper fill deposition is considered the most difficult part of the damascene process. At present, 0.25-micron wide vias and holes 1 micron deep are hard to fill completely without forming voids or small cracks. Yet, to facilitate closer packing and multilevel connections, trenches are getting proportionally deeper as they get narrower. With current technology, the deeper the trench, the more likely there will be defects. The goal is to get from 250 nanometers to 100 nanometers, at a 10-to-1 aspect ratio, far beyond the reach of current practice.
Multilayer IC architectures can be metallized using xe2x80x9cdual-damascenexe2x80x9d methods in which successive layers are built upon one another. Although such multilayer architectures are now deemed essential, it is currently said by some in the industry that xe2x80x9cusing copper is a multi-damascene integration nightmare.xe2x80x9d Yield is a touchy subject for fabrication plants, and hard data on copper production has yet to be disclosed. But it appears early results are disappointing. Critical flaws such as gaps in copper lines have brought yields for some operations down to well below acceptable levels. The electroplating apparatus disclosed here provides a new approach to metallization that alleviates many of the difficulties described above.
Several aspects of the present invention overcome the difficulties currently encountered in electroforming of metal deposits within the microscopic cavities of lithographically produced plating molds. The invention has two primary areas of application: (1) the LIGA process used to produce complex metal parts having microscopic details and (2) the damascene process used for electroplating the line and via interconnects of microelectronic devices.
In a conventional LIGA electroplating process, the plating rate within individual mold cavities depends upon a multitude of geometric factors such as cavity width dimensions, aspect ratios, spacing, areal density of features, and proximity to mold edges. As a result, overplating occurs in some areas of the mold while other areas remain only partially filled, requiring multiple cycles in which overplated metal is removed, some areas are masked off, and electroplating is resumed. Trapped voids and poor metal morphology are also commonly observed, resulting in lost yield. These difficulties are caused by two primary factors: (1) nonuniform current density resulting from three-dimensional redistribution of electric current in the space between the bath electrode and the mold top, and (2) nonuniform ion transport from the electrolyte bath to the plating surfaces in individual mold features. Similar difficulties arise in the electroplating of microelectronic interconnections.
An aspect of the invention solves the problem of nonuniform current flow by employing a porous electrode positioned adjacent to the plating mold, leaving little or no intervening space for current redistribution. The mold is sandwiched between the porous electrode and the conducting solid substrate on which the metal deposits are formed. Since the LIGA mold is nonconducting, the current flow between the porous electrode and the plating surface is purely one dimensional and the gradient of the electric potential between the top and bottom of the mold must be the same within every mold cavity.
Another aspect of the invention solves the problem of nonuniform transport of metal ions within different mold cavities. Electrolyte is pumped over the external face of the porous electrode to maintain a uniform ion concentration over that surface. However, the porous electrode prevents this external flow from causing electrolyte circulation within individual mold cavities, avoiding preferential enhancement of ion transport in features having favorable geometries such as shallow aspect ratios. By preventing these microscale fluid circulations, the present invention ensures that the ion transport within mold cavities will occur by only two processes, diffusion and ion drift. Since the concentration gradient and the electric field are both one dimensional and the same in each mold cavity, the transport of ionic species and dissolved hydrogen gas will be identical in each feature.
A third aspect of the invention eliminates the problems of ineffective bonding or uneven contact between the plating mold and the substrate that would otherwise lead to unintended underplating of the mold. In one preferred embodiment of the invention, the sandwiched assembly consisting of the porous electrode, mold, and substrate electrode is housed within a plating cell along with a compliant porous spacer that is compressed during assembly to apply the pressure needed to hold all components together. Electrolyte is pumped through the porous spacer to maintain a uniform ion concentration across the exposed dye face of the porous electrode.
In addition to LIGA applications, the invention can also be used for electroplating microelectronic interconnects. Here, the steady progression to smaller line widths requires that the lines become deeper to maintain the same conductance. This increases the aspect ratio, making it very difficult to fill the lines completely before closure occurs at the top of the plating mold which, in this case, is a nonconductive layer that has been patterned by lithograph and etching processes. The conventional damascene process currently used for copper plating requires that a conductive seed layer be applied to the entire surface of the mold, so that the sidewalls of the mold cavities are no longer insulators. Since this aggravates the problem of nonuniform filling, it may be desirable to remove some of the seed layer by a preferential etching process, so that the process become essentially equivalent to LIGA electroplating. Even if the seed layer is left in tact, the present invention can be used to prevent unwanted electroplating on the wafer face and to improve plating uniformity.
In either LIGA or microelectronics applications, the porous electrode can be pre-patterned by applying a patterned impermeable and/or insulating layer to the electrode surface that contacts the mold. This can be used to: (1) control the plating pattern on the substrate, (2) provide a plating mold that is attached to the porous electrode, (3) provide an electrical standoff that prevents shorting of the porous electrode to a conducting mold, or (4) provide a physical standoff to prevent shorting of the porous electrode to metal deposits reaching the top of a nonconducting mold. The pattern of the porous electrode could be produced by silk screening, selective etching, or even by use of addressable pixels that could locally permit or prevent ion transport.